A press release was issued regarding the research results of Professor Ken Takeuchi (Faculty of Science and Engineering; Department of Electrical, Electronic, and Communication Engineering). These research results were announced at the International Memory Workshop (IMW) which was held in Monterey, California (USA) from May 17 to 20, 2015.
Using machine learning to predict errors in ReRam (resistance random access memory) and realize a thirteen-fold increase in memory lifespan
My research team has succeeded in using machine learning to predict errors in ReRam (resistance random access memory) and realized a thirteen-fold increase in memory lifespan (number of times for which overwriting is possible). Today, from mobile phones to data center storage, there is widespread use of SSD which utilize flash memory as a storage medium. Although flash memory has the benefit of large capacity, it also has the problem of slow overwriting at 1 millisecond (10-3 seconds). Conversely, ReRam enables overwriting at 100 nanoseconds (10-9 seconds), which is ten thousand times faster than flash memory. However, repeated overwriting of data causes defects of ReRam memory cells which store data and results in damage to the stored data. In our research, my team used a machine learning algorithm to predict future fatigue of ReRam memory cells based on past records, thus developing a method for distinguishing between defective memory cells which malfunction completely (hard error) and memory cells which recover normal function when rewritten after malfunction (soft error). This now makes it possible to predict defective memory cells (hard error) in advance. Furthermore, by rewriting memory cells which will become defective into normally functioning memory cells before the defect occurs, we succeeded in containing defects in advance. Using this technology, we succeeded in realizing a thirteen-fold increase in the normal lifespan (number of times for which overwriting is possible) of ReRam. Using ReRam for storage in mobile devices, motor vehicles and data centers will enable high-speed, high-reliability recording and processing of data. Accordingly, we expect the realization of services providing high-speed real-time response, such as automatic driving and Industry 4.0.
This research was supported by the JST Strategic Basic Research Programs CREST and was implemented as part of the Highly reliable low power VLSI memory system research project by the Chuo University Center for Research and Development Initiatives.
Click here for detailed press release (PDF: 503kb)
Green-Nano LSI Circuit System Takeuchi Laboratory